In general, flash memory devices, which are nonvolatile memory devices, comprise a stacked structure of a floating gate and a control gate. An element isolation process for isolating elements is performed between the floating gates. Such an element isolation process is performed on a substrate before a process of forming the floating gates, and a shallow trench isolation (STI) process is typically used to isolate the elements.
When the element isolation is implemented using the STI process, the floating gate overlaps the STI element isolation film. The overlapping of the floating gate on the STI element isolation film causes reduction of the element area such that the size reduction of a cell array is obstructed or inhibited. Specifically, in the conventional element isolation process such as the STI process of isolating the elements in a flash memory cell region, a silicon nitride film is deposited, a patterning process of forming a field region is performed, a dry etching process is performed, a chemical vapor deposition (CVD) process is performed with an insulating material, a polishing process is performed, and a wet etching process of etching the deposited silicon nitride film is then performed.
A flash gate process is performed after the element isolation process. Specifically, after the element isolation process, the floating gate forming process is performed as the flash gate forming process. Because the floating gate process is performed after the element isolation process, the floating gates must share a portion of the insulating element isolation film made of an insulating material for reliable isolation. The shared portion affects the cell size, thereby causing a problem in the flash memory device of which the cell size is particularly important.